Compensating threads for microarchitectural resource contentions by prioritizing scheduling and execution
US9244732B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2009 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | Sep 12, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/486
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A thread (or other resource consumer) is compensated for contention for system resources in a computer system having at least one processor core, a last level cache (LLC), and a main memory. In one embodiment, at each descheduling event of the thread following an execution interval, an effective CPU time is determined. The execution interval is a period of time during which the thread is being executed on the central processing unit (CPU) between scheduling events. The effective CPU time is a portion of the execution interval that excludes delays caused by contention for microarchitectural resources, such as time spent repopulating lines from the LLC that were evicted by other threads. The thread may be compensated for microarchitectural contention by increasing its scheduling priority based on the effective CPU time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.