Parallelization of error analysis circuitry for reduced power consumption
US9244765B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2011 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | Aug 30, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6561
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory device (e.g., a flash memory device) includes power efficient codeword error analysis circuitry. The circuitry analyzes codewords stored in the memory of the memory device to locate and correct errors in the codewords before the codewords are communicated to a host device that requests the codewords from the memory device. The circuitry includes a highly parallel configuration with reduced complexity (e.g., reduced gate count) that a controller may cause to perform the error analysis under most circumstances. The circuitry also includes an analysis section of greater complexity with a less parallel configuration that the controller may cause to perform the error analysis less frequently. Because the more complex analysis section runs less frequently, the error analysis circuitry may provide significant power consumption savings in comparison to prior designs for error analysis circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.