Variable data recovery scheme hierarchy
US9244766B2 · kind B2 · utility
11Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2013 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | Dec 28, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory has a plurality of solid-state non-volatile memory cells. A processing circuit is connected to the memory and configured to direct the execution of a plurality of read error recovery routines in response to at least one uncorrectable read error in a data set retrieved from the memory. The recovery routines are executed in a selected order based on an elapsed recovery time parameter for each of the recovery routines and an estimated probability of success of each of the recovery routines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.