Reduced level cell mode for non-volatile memory
US9245653B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2013 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | Apr 12, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses, systems, methods, and computer program products are disclosed for reduced level cell solid-state storage. A method includes determining that an erase block of a non-volatile storage device is to operate in a reduced level cell (RLC) mode. The non-volatile storage device may be configured to store at least three bits of data per storage cell. A method includes instructing the non-volatile storage device to program first and second pages of the erase block with data. A method includes instructing the non-volatile storage device to program a third page of the erase block with a predefined data pattern. Programming of a predefined data pattern may be configured to adjust which abodes of the erase block are available to represent stored user data values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.