Memory circuit structure and semiconductor process for manufacturing the same
US9245766B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2014 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | May 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor process for manufacturing particular patterns includes the steps of forming a target layer and evenly-spaced core bodies on a substrate, conformally forming a hard mask layer, forming a first photoresist covering a predetermined region on the hard mask layer wherein the predetermined region encompasses at least two core bodies, performing a first etch process to remove a portion of the hard mask layer outside the predetermined region and expose a number of core bodies, removing the exposed core bodies, forming a second photoresist at least encompassing all the recesses in the predetermined region, and performing a second etch process to pattern the target layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.