Time-to-voltage converter using a capacitor based digital to analog converter for quantization noise cancellation
US9246500B2 · kind B2 · utility
20Cited by
7References
25Claims
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Key dates
| Filing date | Jul 31, 2014 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | Jul 31, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3004
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Quantization noise in a fractional-N phase-locked loop (PLL) is canceled using a capacitor-based digital to analog converter (DAC). A phase error is detected between a reference signal and a feedback signal in the PLL. A charge pump circuit charges a first capacitor circuit based on the phase error to generate a phase error voltage corresponding to the phase error. The capacitor based DAC generates a quantization error correction voltage based on a digital value corresponding to the quantization error, which is then combined with the phase error voltage to cancel the quantization error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.