Error correction code block having dual-syndrome generator, method thereof, and system having same
US9246515B2 · kind B2 · utility
5Cited by
6References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2011 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | Oct 16, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6561
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An error correction code block including dual-syndrome generators, which may process a plurality of successive code word without latency, is configured to calculate syndrome values of a corresponding even numbered codeword among the plurality of code words by using one of the dual-syndrome generators, and is configured to calculate syndrome values of a corresponding odd numbered codeword among the plurality of code words by using the other of the dual-syndrome generators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.