Test pattern optimization for LDPC based flawscan
US9246519B2 · kind B2 · utility
1Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Nov 8, 2012 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | Dec 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6343
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for producing a LDPC encoded test pattern for media in a LDPC based drive system includes adding error detection code data to a predominantly zero bit test pattern and adding additional zero bits to produce a test pattern of a desirable length. The test pattern may then be scrambled to produce a desirable flaw detection test pattern. The flaw detection test pattern may then be encoding with an LDPC code, or other error correction code with minimal disturbance to the run length constraints of the data pattern, and written to a storage medium.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.