Method and apparatus for clock recovery
US9246667B2 · kind B2 · utility
0Cited by
2References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 7, 2014 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | Mar 7, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device may have an internal oscillator for generating a system clock, a trimming logic with a trimming register for adjusting an oscillation frequency of the internal oscillator; a serial data receiver, wherein a serial data stream includes a synchronization signal. The synchronization signal is operable to indicate that the system clock correct, too fast or too slow. The device may further have a circuit for decoding the synchronization signal operable to re-adjust a value stored in the trimming register upon evaluation of the synchronization signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.