Method, system, and computer program product for implementing a microprocessor with a customizable register file bypass network
US9250900B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2014 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Oct 1, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for implementing a microprocessor with a selective register file bypass network are disclosed. Late bypasses are removed from a register file bypass network of a microprocessor design. One or more late bypasses are then added back to the register file bypass network based at least in part upon the results of analyzing a plurality of instructions that are to be processed in an instruction pipeline of the microprocessor. An electronic design for at least the register file bypass network is then generated with these one or more late bypasses that are added to the register file bypass network. Without incurring additional hardware or cost for the microprocessor design, one or more bypasses in the register file bypass network may be optionally shared among multiple free-riders, and an entire port stage may also be optionally bypassed to another port stage based upon one or more criteria.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.