Virtualizing processor memory protection with “L1 iterate and L2 drop/repopulate”
US9251102B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2014 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Aug 18, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/151
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system includes a guest domain access control register (DACR), and guest first and second level page tables, the page tables containing domain identifiers used to obtain domain access information and access permission information, and the domain access information and the access permission information providing an effective guest access permission. The computing system provides a shadow page table, in which domain identifiers are used to identify domain access information in a processor DACR that are mapped from domain access information in the guest DACR, and in which access permissions are mapped from effective access permission information in the guest page tables and guest DACR. A memory management unit in the processor traverses the shadow page table, accesses the processor DACR, and combines the mapped domain access information in the processor with the mapped access permission in the shadow page table to reflect the guest intended effective access permissions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.