Scheduling computation processes including all-to-all communications (A2A) for pipelined parallel processing among plurality of processor nodes constituting network of n-dimensional space
US9251118B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2010 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | May 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/329
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Optimally scheduling a plurality of computation processes including all-to-all communications (A2A) among a plurality of nodes (processors) constituting an n-dimensional (a torus or a mesh) network.The plurality of nodes (processors) constituting the network are divided into a communication (computation process) phase (A2A-L) required for all-to-all communications only among a plurality of nodes included in a first subgroup and a communication (computation process) phase (A2A-P) required for all-to-all communications only among a plurality of nodes included in a second subgroup to perform parallel processing with the phases overlapped with each other across a plurality of threads (thread 1, thread 2, thread 3, and thread 4). It is also possible to perform the parallel processing with respect to a plurality of computation processes such as a fast Fourier transform (FFT) and a transpose (T) (internal transpose).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.