Cost effective low pin/ball count level-shifter for LCD bias applications supporting charge sharing of gate lines with perfect waveform matching
US9251753B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2013 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Apr 17, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/023
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A level shifter circuit has a plurality of channels for providing signals to a capacitive load and has circuits for sharing charge stored in the capacitive load between the channels. A first pair of channel clock generating circuits are coupled respectively to a first pair of channels. A second pair of channel clock generating circuits are coupled respectively to a second pair of channels. A pair of switches couple the first pair of channels together and the second pair of channels together, respectively, for sharing charge between the channels. A single resistor is coupled in circuit with all of the channels for controlling a slope of charge sharing between channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.