High voltage driver using medium voltage devices
US9252651B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2012 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Oct 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/6872
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A voltage drive circuit is constructed by stacking NMOS and PMOS transistors to provide high voltage levels with an output voltage swing greater than the breakdown voltage of the individual transistors used to build the voltage drive circuit. The voltage drive circuit may include a series stack of capacitors connected between gates of the stacked PMOS and NMOS transistors. The capacitive loading causes the gate signals to change more synchronously. Errors in timing for these gate signals, which would otherwise result in damage from exceeding the breakdown voltage across a pair of terminals of one of the NMOS and PMOS transistors, are mollified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.