Bias circuits and methods for stacked devices
US9252713B2 · kind B2 · utility
2Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2014 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Jun 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/61
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure include a bias circuit for generating bias voltages to stacked transistors. In one embodiment, stacked transistors are coupled between an input transistor and an output node. A modulated power supply voltage and an input signal produce a voltage at the output node. The modulated power supply voltage is provided as an input to the bias circuit. Bias voltages are generated that change with the power supply voltage. In one embodiment, particular transistors in the stack are biased so that their control terminals are effectively short circuited when the power supply voltage is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.