Phase error detection in phase lock loop and delay lock loop devices
US9252788B1 · kind B1 · utility
5Cited by
62References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2014 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Sep 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device includes a lock detect circuit that is structured and arranged to: convert a reference clock to a reference triangle wave; convert a feedback clock to a feedback triangle wave; determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; and generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.