Low latency serial data encoding scheme for enhanced burst error immunity and long term reliability
US9252812B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2014 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | May 10, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4908
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A high performance computing system and method communicate data packets between computing nodes on a multi-lane communications link using a modified header bit encoding. Each data packet is provided with flow control information and error detection information, then divided into per-lane payloads. Sync header bits for each payload are added to the payloads in non-adjacent locations, thereby decreasing the probability that a single correlated burst error will invert both header bits. The encoded blocks that include the payload and the interspersed header bits are then simultaneously transmitted on the multiple lanes for reception, error detection, and reassembly by a receiving computing node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.