Power efficient driver architecture
US9252833B2 · kind B2 · utility
0Cited by
14References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 7, 2012 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Dec 8, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/583
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Disclosed are various embodiments for providing a power-efficient driver architecture supporting rail-to-rail operation in full duplex mode. A driver is configured to drive a duplex signal over a transmission medium. A hybrid is configured to recover a received signal from the duplex signal. The received signal is generated by a remote transceiver. The driver is configured to drive the duplex signal based at least in part on the received signal recovered by the hybrid.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.