Matrix router and method of switching
US9253118B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Jan 15, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/1515
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A matrix router and method of switching comprising a combined input stage and output stage (I/O stage) having m matrix switch(es), each matrix switch having n inputs and n outputs, each input of said n inputs switchable within said matrix switch to any output of said n outputs, k core outputs and k core inputs, each input of said n inputs switchable to any core output of said k core outputs and each core input of said k core inputs switchable to any output of said n outputs; and a core stage having a matrix switch at least with m times k core stage inputs and at least m times k core stage outputs, each core stage input connected to one core output of said I/O stage, and each core stage output connected to one core input of said I/O stage, where m, n and k are integers and m≧1, n≧2, k≧n.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.