Clock tree circuit and memory controller
US9256245B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2015 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Jan 22, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock tree circuit includes a clock source and a tree circuit. The clock source generates a signal. The tree circuit at least includes five driving units and a metal connection element. A first driving unit has an input terminal for receiving the signal, and an output terminal coupled to a first node. A second driving unit has an input terminal coupled to the first node, and an output terminal coupled to a second node. A third driving unit has an input terminal coupled to the first node, and an output terminal coupled to a third node. A fourth driving unit has an input terminal coupled to the second node. A fifth driving unit has an input terminal coupled to the third node. The metal connection element is coupled between the second node and the third node, and configured as a short-circuited element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.