Programmable memory controller
US9256369B2 · kind B2 · utility
8Cited by
1References
30Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Apr 18, 2013 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Mar 31, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment includes a programmable memory controller. The programmable memory controller includes a request processor that comprises a first domain-specific instruction set architecture (ISA) for accelerating common requests. A transaction processor comprises a second domain-specific ISA for accelerating transaction processing tasks. A dedicated command logic module inspects each memory command to a memory device and stalls particular commands for meeting timing constraints for application specific control of the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.