Method and apparatus for controlling power in low-power multi-core system
US9256508B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2010 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Apr 25, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for controlling power in a low-power multi-core system, including receiving task information from an Operation System (OS) kernel upon start and end of a task, estimating a future CPU usage using a current CPU usage in the task information, monitoring memory-related information in the task information, comparing a change in the current CPU usage with the monitored memory-related information, establishing a policy for power control based on the estimated CPU usage and the monitored memory-related information, and controlling on/off of multiple cores according to the established policy. By doing so, it is possible to solve the problems caused by performing DPM using only the CPU usage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.