Method and apparatus for providing shared caches
US9256536B2 · kind B2 · utility
1Cited by
4References
22Claims
0Family size
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Key dates
| Filing date | Apr 30, 2013 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Dec 13, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for providing shared caches. A cache memory system may be operated in a first mode or a second mode. When the cache memory system is operated in the first mode, a first cache and a second cache of the cache memory system may be operated independently. When the cache memory system is operated in the second mode, the first cache and the second cache may be shared. In the second mode, at least one bit may overlap tag bits and set index bits among bits of a memory address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.