Method and system for automatic generation of solutions for circuit design rule violations
US9256708B2 · kind B2 · utility
1Cited by
9References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 17, 2010 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Nov 17, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments provide a method for automatically generating several design solutions that remedy a design rule violation committed by a set of shapes in an IC design layout. The method receives a marker that indicates the design rule violation and contains information about the violation. The marker in some embodiments can be rendered as a geometric shape in the IC design layout. Based on the marker, the method generates several solutions each of which will cause the set of shapes to meet the design rule when the solution is applied to the set. Each solution requires moving at least one edge of a shape in the set of shapes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.