Integrated circuit device, method for producing mask layout, and program for producing mask layout
US9257367B2 · kind B2 · utility
0Cited by
12References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 19, 2013 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Nov 29, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a method for producing a mask layout of an exposure mask for forming wiring of an integrated circuit device, includes estimating shape of the wiring formed based on an edge of a pattern included in an initial layout of the exposure mask. The method includes modifying shape of the edge if the estimated shape of the wiring does not satisfy a requirement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.