Semiconductor device
US9257371B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2015 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Mar 12, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is reduced in size. The semiconductor device includes a die pad, a plurality of leads arranged around the die pad, a memory chip and a power source IC chip mounted over the die pad, a logic chip mounted over the memory chip, a plurality of down bonding wires for connecting the semiconductor chip to the die pad, a plurality of lead wires for connecting the semiconductor chip to leads, and a plurality of inter-chip wires. Further, the logic chip is arranged at the central part of the die pad in a plan view, and the power source IC chip is arranged in a corner part region of the die pad in the plan view. This reduces the size of the QFN.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.