Self-aligned implantation process for forming junction isolation regions
US9257463B2 · kind B2 · utility
1Cited by
13References
20Claims
0Family size
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Key dates
| Filing date | Aug 17, 2012 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Feb 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/807
Abstract
A device includes a semiconductor substrate, a well region in the semiconductor substrate, and a Metal-Oxide-Semiconductor (MOS) device. The MOS device includes a gate dielectric overlapping the well region, a gate electrode over the gate dielectric, and a source/drain region in the well region. The source/drain region and the well region are of opposite conductivity types. An edge of the first source drain region facing away from the gate electrode is in contact with the well region to form a junction isolation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.