Patent · US Active

Circuit arrangement for protecting electronic devices against incorrect logic voltages

US9257897B2 · kind B2 · utility

2Cited by

16References

5Claims

0Family size

Assignee

PHOENIX CONTACT GMBH & CO. KG · DE

Inventors

Klaus-Peter Saeck · Detmold, DE
Thomas Warneke · Ennigerloh, DE
Viktor Oster · Blomberg, DE

Key dates

Filing date	Oct 23, 2009
Grant date	Feb 9, 2016
Priority date	—
Expiry date	Jul 19, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH02M3/02
WIPO fieldElectrical machinery, apparatus, energy
WIPO sectorElectrical engineering

Abstract

The invention is based on the problem of devising a circuit arrangement (10) for protecting electronic devices from incorrect logic voltages, wherein this circuit arrangement delivers increased protection against overvoltages, so that this circuit arrangement could also be used in multi-channel fail-safe systems that satisfy, for example, Performance Level “e” according to DIN EN ISO 13849. The circuit arrangement (10) has an input terminal (80) for connecting a power supply device and at least one voltage converter (90) that delivers, on the output side, an adjustable logic voltage. A controllable switching element (70) is connected between the one or more voltage converters (90, 95) and the input terminal (80). Furthermore, a first monitoring device (20) is provided for monitoring the logic voltage. The first monitoring device (20) is constructed so that it triggers the opening of the switching element (70) when the logic voltage reaches or exceeds a predetermined threshold.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.