High-speed frequency divider
US9257991B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 21, 2014 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Aug 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/68
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable high-speed frequency divider architecture is provided that is programmable to divide an input clock signal frequency by a selectable division N. The frequency divider architecture has a shift register circuit having N/2 shift register stages, connected in series when N is an even integer and trunc[N/2]+1 shift register stages when N is an odd integer. The frequency divider architecture includes a feedback logic circuit that performs a logical NAND of the output clock signal with the logical ORed result of a pre-output signal provided from a shift register stage prior to the output stage and another signal that indicates whether the selectable divisor N is odd or even.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.