Wafer level integrated circuit contactor and method of construction
US9261537B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2013 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Jun 20, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49204
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A testing device for wafer level testing of IC circuits is disclosed. An upper and lower pin (22, 62) are configured to slide relatively to each other and are held in electrically biased contact by an elastomer (80). The elastomer is precompressed from its natural rest state between a top (22) plate and a bottom (70). Pre compression improves the resilient response of the pins. The pin crows (40) are maintained relatively coplanar by the engagement of at least one flang (44a-b) against an up-stop surface 90 of plate 20, thereby insuring coplanarity of the crowns. The pin guide (12) is maintained in alignment with the retainer 14 by establishing a registration corner (506) and driving the guide into the corner by elastomers in at least one diagonally opposite corner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.