Array substrate, method for fabricating the same and liquid crystal panel
US9261750B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Jun 5, 2013 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Jun 5, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/13685
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate, a method for fabricating the same and a liquid crystal panel are disclosed. The array substrate includes a display region and a frame region surrounding the display region. The display region includes a plurality of data lines, a plurality of scan lines and a plurality of scan connection lines. The plurality of data lines and the plurality of scan lines intersect each other to divide the display region into a plurality of pixel regions. The plurality of scan lines are electrically connected to the plurality of scan connection lines in a one-to-one correspondence in the display region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.