Memory system controlling peak current generation for a plurality of memories by monitoring a peak signal to synchronize an internal clock of each memory by a processor clock at different times
US9261940B2 · kind B2 · utility
4Cited by
1References
10Claims
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Key dates
| Filing date | Feb 15, 2012 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Jun 12, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.