Non-volatile memory channel control using a general purpose programmable processor in combination with a low level programmable sequencer
US9262084B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2015 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Jun 3, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a device interface, a micro-sequencer, and a programmable sequence memory. The device interface may be configured to process a plurality of read/write operations to/from one or more non-volatile memory devices. The micro-sequencer may be configured to communicate with the device interface. The programmable sequence memory is generally readable by the micro-sequencer. In response to the apparatus receiving a command, (a) the micro-sequencer executes a set of instructions starting at a location in the programmable sequence memory according to the command and (b) the micro-sequencer is enabled to perform at least a portion of the command according to a protocol of the one or more non-volatile memory devices, when the one or more non-volatile memory devices are coupled to the device interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.