Vector processor and vector processor processing method
US9262165B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2013 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Jul 17, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3887
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A vector processor includes an instruction fetching unit configured to acquire an instruction, a decoding/issuing unit configured to decode the instruction and issuing the instruction, an operation group configured to include a plurality of operation units and a register configured to store the element data column, wherein the plurality of operation units include a first operation unit processes a first type instruction and a second operation unit processes a second type instruction and the first type instruction; and when a plurality of divided instructions, for which the element data of an instruction to be issued has been divided, are processed by the second operation unit, in a case where the second type instruction is not present, the decoding/issuing unit issues the divided instructions, and in a case where the second type instruction is present, the decoding/issuing unit issues the instruction to be issued without performing division.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.