Single channel memory mirror
US9262284B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2006 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Jul 11, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention address deficiencies of the art in respect to memory fault tolerance, and provide a novel and non-obvious method, system and apparatus for single channel memory mirroring. In one embodiment of the invention, a single channel memory mirroring system can be provided. The single channel memory mirroring system can include a memory controller, a single communications channel, and an operational data portion of memory, and a duplicate data portion of memory, both portions being communicatively coupled to the memory controller over the single communications channel. Finally, the system can include single channel memory mirror logic. The logic can include program code enabled to mirror data in the operational data portion of memory in the duplicate data portion of memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.