Privileged mode methods and circuits for processor systems
US9262340B1 · kind B1 · utility
3Cited by
7References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2011 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Apr 27, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1491
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system can include a processor coupled to a bus; a first memory coupled to the bus, configured to limit access to a privileged portion according to at least protection values; a second memory coupled to the bus and having a privileged supervisory portion configured to be section erasable, access to the second memory being limited according to at least the protection values; and a boot sequence stored in the privileged portion that configures the processor to decode values stored in the supervisory portion into the protection values for storage in protection value registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.