Apparatus and method for accelerated page link list processing in a packet processor operating at wirespeed
US9262369B1 · kind B1 · utility
0Cited by
9References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 1, 2015 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Apr 1, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/25
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A packet processor has a packet memory manager configured to store a page walk link list, receive a descriptor and initiate a page walk through the page walk link list in response to the descriptor and without a prompt from transmit direct memory access circuitry. The packet memory manager is configured to receive an indicator of a single page packet and read a new packet in response to the indicator without waiting to obtain page state associated with the page of the single page packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.