Memory systems including an input/output buffer circuit
US9263105B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2013 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Jan 10, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory systems are provided. A memory system may include a plurality of nonvolatile memories and a memory controller configured to control the plurality of nonvolatile memories. Moreover, the memory system may include an input/output buffer circuit connected between the memory controller and the plurality of nonvolatile memories. A data channel may be connected between the memory controller and the input/output buffer circuit, and first and second internal data channels may be connected between the input/output buffer circuit and respective first and second groups of the plurality of nonvolatile memories. The input/output buffer circuit may be configured to connect the data channel to one of the first and second internal data channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.