Low power transient voltage collapse apparatus and method for a memory cell
US9263121B2 · kind B2 · utility
13Cited by
6References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 16, 2013 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Aug 23, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/414
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described is an apparatus for memory write assist which consumes low power during write assist operation. The apparatus comprises: a power supply node; a device operable to adjust voltage on the power supply node; and a feedback unit coupled to the power supply node, the feedback unit to control the device in response to a voltage level of the voltage on the power supply node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.