Capping poly channel pillars in stacked circuits
US9263459B1 · kind B1 · utility
11Cited by
1References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2014 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Sep 26, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three dimensional or stacked circuit device includes a conductive channel cap on a conductor channel. The channel cap can be created via selective deposition or other process to prevent polishing down the conductive material to isolate the contacts. The conductor channel extends through a deck of multiple tiers of circuit elements that are activated via a gate. The gate is activated by electrical potential in the conductor channel. The conductive cap on the conductor channel can electrically connect the conductor channel to a bitline or other signal line, and/or to another deck of multiple circuit elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.