Component, for example NMOS transistor, with active region with relaxed compression stresses, and fabrication method
US9263518B2 · kind B2 · utility
6Cited by
5References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2014 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Jun 10, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a substrate and at least one NMOS transistor having, in the substrate, an active region surrounded by an insulating region. The insulating region is formed to includes at least one area in which the insulating region has two insulating extents that are mutually separated from each other by a separation region formed by a part of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.