Oxide transistor with nano-layered structure
US9263592B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2013 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Sep 7, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6757
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor includes source/drain electrodes provided on a substrate; a semiconductor oxide layer provided between the source/drain electrodes; a gate electrode facing the semiconductor oxide layer; and a gate insulating layer interposed between the semiconductor oxide layer and the gate electrode, wherein the semiconductor oxide layer has a nano-layered structure including at least one first nano layer comprised of a first material and at least one second nano layer comprised of a second material that are alternatingly stacked one on another to provide at least one interface, and wherein the first material and the second material are different materials that are effective to form an electron transfer channel layer at the interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.