Information processing device including host device and semiconductor memory device having plurality of address conversion information
US9268706B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2012 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Jan 7, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.