Parallel bit reversal devices and methods
US9268744B2 · kind B2 · utility
0Cited by
3References
10Claims
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Assignee
Inventors
Key dates
| Filing date | Dec 31, 2011 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Oct 21, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/768
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel bit reversal device and method. The device includes a parallel bit reversal unit, a butterfly computation and control unit, and a memory. The butterfly computation and control unit is coupled to the memory via a data bus. The parallel bit reversal unit is configured to bit-reverse butterfly group data used by the butterfly computation and control unit. The parallel bit reversal unit includes an address reversing logic coupled to the butterfly computation and control unit, and configured to perform mirror reversal and right-shift operations on a read address from the butterfly computation and control unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.