Volume rendering on shared memory systems with multiple processors by optimizing cache reuse
US9269123B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 3, 2013 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Apr 1, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2210/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system and product are disclosed for volume rendering of medical images on a shared memory system implemented on a multi-socket mainboard with multiple multi-core processors and multiple last level caches, cores that share a cache being united in a socket. The method includes decomposing the image space to be used for rendering in regions, each region including a plurality of tiles; assigning two sockets to each of the decomposed regions; determining a tile enumeration scheme for a region; rendering all tiles within a region according to a determined tile enumeration scheme on the assigned two sockets until the respective region is finished; if a region is finished, assigning the two sockets to another region; and if no region is left, splitting an existing region of un-rendered tiles into sub-regions according to a splitting scheme and applying the steps recursively for the sub-regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.