Shift register unit, gate driving circuit and display apparatus
US9269289B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 11, 2013 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Mar 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0219
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A shift register unit, a gate driving circuit and a display apparatus are disclosed. The shift register unit includes a first TFT (T1) having a first electrode connected to an input terminal and a gate connected to a second clock signal input terminal; a second TFT (T2); a third TFT (T3) having a second electrode connected to an output terminal, a first electrode connected to a first clock signal input terminal, and a gate connected to the second electrode of the first TFT; a fourth TFT (T4); a fifth TFT (T5) having a gate connected to the second clock signal input terminal, a first electrode connected to the output terminal and a second electrode connected to the low potential connecting terminal; a capacitor (C1), and thus the burrs and miscellaneous spikes in a gate driving waveform outputted by the circuit can be suppressed well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.