Latch-based memory array
US9269423B2 · kind B2 · utility
29Cited by
7References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 10, 2013 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Mar 9, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention concerns a memory array having memory cells arranged in columns and rows, the memory cells of each column being coupled to at least one common write line of their column, the memory cells of each row being coupled to a common selection line of their row, wherein each of the memory cells includes a latch formed of a pair of inverters cross-coupled between first and second storage nodes; a first transistor coupled between the first storage node and a first test data input; and a second transistor coupled between the second storage node and a second test data input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.