System and method for intelligently flushing data from a processor into a memory subsystem
US9269438B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2011 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Dec 25, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method are described for intelligently flushing data from a processor cache. For example, a system according to one embodiment of the invention comprises: a processor having a cache from which data is flushed, the data associated with a particular system address range; and a PCM memory controller for managing access to data stored in a PCM memory device corresponding to the particular system address range; the processor determining whether memory flush hints are enabled for the specified system address range, wherein if memory flush hints are enabled for the specified system address range then the processor sending a memory flush hint to a PCM memory controller of the PCM memory device and wherein the PCM memory controller uses the memory flush hint to determine whether to save the flushed data to the PCM memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.