Thin film transistor array panel and manufacturing method thereof
US9269726B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2014 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Jan 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/021
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A thin film transistor (TFT) array panel and a manufacturing method thereof are disclosed. A contact hole may be formed to expose a pad disposed on a substrate of the TFT array panel. A first layer of a connecting member is formed with the same layer as a first field generating electrode and is disposed in the contact hole. A second passivation layer is disposed in the TFT array panel, but is removed at a region where the contact hole is formed and portions of the second passivation layer that cover the first layer of the connecting member. A second layer of the connecting member is formed on the first layer of the connecting member.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.