Guard ring for memory array
US9269766B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2014 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Sep 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device and a method for forming a device are presented. The method includes providing a substrate having an array region in which memory cells are to be formed. Storage gates of the memory cells are formed in the array region. A guard ring surrounding the array region is formed. A gate electrode layer is formed on the substrate. The gate electrode layer fills gaps between the storage gates and guard ring. The gate electrode layer is planarized to produce a planar surface between the gate electrode layer, storage gates and guard ring. The guard ring maintains thickness of the gate electrode layer in the array region such that thickness of the storage gates across center and edge regions of the array region is uniform.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.